X6-RX

INNOVATIVE INTEGRATION

Innovative Integration X6-RX - PMC/XMC Module with Four 160 MSPS A/Ds, ASIC downconverter, Virtex6 FPGA, 4 GB Memory and PCI/PCIe Simple Type: Mezzanine Card The X6-RX is a flexible receiver that integrates IF digitizing with signal processing on a PMC IO module. The module provides up to 24 configurable receiver channels with a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. With the X6-RX, IF recorders can log both the digitized raw data and channels real-time sustaining rates over 2 GB/s. The X6-RX features four, 16-bit 160 MSPS A/Ds with dual digital downconverters (DDC). IF frequencies of up to 300 MHz are supported. The sample clock is from either a low-jitter PLL or external input. Multiple cards can be synchronized for sampling and downconversion. A Xilinx Virtex6 SX315T (LX240T at initial release) with 4 banks of 128MB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates. Onboard DDC ASIC device, connected directly to the FPGA, provides up to 24 narrowband or 8 wideband channels with input from two A/D channels. The DDC performs complex or real downconversion, with flexible controls for mixing, filtering, decimation, output formats and data rates. Channels can be synchronized to support beam forming or frequency hopped systems. The X6 family power is less than 15W for typical operation. VITA 20 conduction cooling is used with a heat-spreader and sink are Ruggedization levels for wide-temperature operation and conformal coating are supported. The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic toolset. The MATLAB BSP supports real-time hardware-inthe-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP cores for DDC, demodulation, and FFT are available. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided. Download the datasheet (PDF)

X6-400M

INNOVATIVE INTEGRATION

Innovative Integration X6-400M - PMC/XMC Module with Two 400/500 MSPS A/Ds, Two 500 MSPS DACs, Virtex6 FPGA, 4 GB Memory and PCI/PCIe Simple Type: Mezzanine Card The X6-400M integrates high speed digitizing and signal generation with signal processing on a PMC/XMC IO module with a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. The X6-400M features two 14-bit 400MSPS or 12-bit 500 MSPS A/Ds, either AC or DC-coupled, plus two 500MSPS update rate DACs. The DAC can be used a single 1 GHz output channel. Analog IO is either AC or DC coupled. Receiver IF frequencies of up to 250 MHz are supported. The sample clock is from either a low-jitter PLL or external input. Multiple cards can be synchronized for sampling. A Xilinx Virtex6 LX240T (LX315T and SX475T options) with 4 banks of 1GB DRAM provides a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates. The X6-400M power consumption is 19W for typical operation. The module may be conduction cooled using VITA20 standard and a heat spreading plate. Ruggedization levels for wide-temperature operation from -40 to +85C operation and 0.1 g2/Hz vibration. Conformal coating is available. The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic tool set. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical block diagram Simulink environment with Xilinx System Generator. IP cores for many wireless and DSP functions such as DDC, PSK/FSK demod, OFDM receiver, correlators and large FFT are available. Software tools for host development include C++ libraries and drivers for Windows, Linux and VxWorks. Application examples demonstrating the module features are provided. Download the datasheet (PDF)

X5-TX

INNOVATIVE INTEGRATION

Innovative Integration X5-TX - PCIe XMC Module - Four 500 MSPS or Dual 1 GSPS, 16-bit DACs, Virtex5 FPGA with 512MB DDR2 DRAM and 4 MB QDR SRAM Memories Simple Type: Mezzanine Card The X5-TX is an XMC I/O module featuring four channels of 500 MSPS, 16-bit DAC outputs with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface. The DAC devices also support a mode providing two channels at a true 1 GSPS, 16-bit rate without interpolation. A Xilinx Virtex5 SX95T or LX155T with 512 MB DDR2 DRAM and 4MB QDR-II memory provides a very high performance DSP core for demanding applications such RADAR and direct RF digitizing. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 300 GMAC/s. The X5 XMC modules couple Innovative's powerful Velocia architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with >1.6 GB/s capacity using P16 are provided for system integration. The X5 family can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP logic cores are also available for SDR applications that provide multi channel modulations for PSK and FSK systems. These IP cores transform the X5-TX module into versatile transmitter, ready for integration into your application.

X5-RX

INNOVATIVE INTEGRATION

Innovative Integration X5-RX - PCI Express XMC Module with Four 200 MSPS 16-bit A/Ds, Virtex5 FPGA, 512MB DRAM/ 4MB SRAM Simple Type: Mezzanine Card The X5-RX is a high performance digitizing and signal processing module for wireless, RADAR and medical imaging applications. The FPGA computing core supports real-time, 200 MHz signal acquisition and processing for channelization, down-conversion and spectral analysis. For digitizing, the module features four simultaneously sampling 16-bit, 200 MSPS A/Ds. A Xilinx Virtex5 SX95T with 512MB DDR2 DRAM and 4MB QDR-II memory provide a very high performance DSP core that is tightly integrated with the I/O and PCI Express interface. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates exceeding 300 GMACs per second. The X5 XMC modules couple Innovative's powerful Velocia architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with > 1.6 GB/s capacity using P16 are provided for system integration. The X5 family logic can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP libraries for the FPGA are also available for down-conversion and channelization of up to 4096 simultaneous channels, baseband demodulation for PSK, FSK and MSK, and spectral analysis. MATLAB simulation models are provided that support logic integration in to the X5-RX Framework Logic. Download the datasheet (PDF)

X5-G12

INNOVATIVE INTEGRATION

Innovative Integration X5-G12 - PCI Express XMC Module with Dual channel 1 GSPS,12-bit Digitizer, Virtex5 FPGA and 512MB Memory Simple Type: Mezzanine Card The X5-G12 is an XMC I/O module featuring dual channels of 1 GSPS 12-bit digitizing with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface. A Xilinx Virtex5 SX95T or LX155T with 512 MB DDR2 DRAM and 4MB QDR-II memory provides a very high performance DSP core for demanding applications such RADAR and direct RF digitizing. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 300 GMAC/s. The X5 XMC modules couple Innovative's powerful Velocia architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with >1.6 GB/s capacity using P16 are provided for system integration. The X5 family can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP logic cores are also available for SDR applications that provide from 16 to 4096 DDC channels. These IP cores transform the X5 modules into versatile receivers using proven logic cores from R-Interface and Innovative, ready for integration into your application. Download the datasheet (PDF)