INNOVATIVE INTEGRATION » X6-RX
Details
| Part Number | X6-RX |
|---|---|
| Manufacturer | INNOVATIVE INTEGRATION |
| Category | PRODUCTS-X |
| Price | Request Quote |
| Lead Time | Request Quote |
Description
Innovative Integration X6-RX - PMC/XMC Module with Four 160 MSPS A/Ds, ASIC downconverter, Virtex6 FPGA, 4 GB Memory and PCI/PCIe Simple Type: Mezzanine Card The X6-RX is a flexible receiver that integrates IF digitizing with signal processing on a PMC IO module. The module provides up to 24 configurable receiver channels with a powerful Xilinx Virtex 6 FPGA signal processing core, and high performance PCI Express/PCI host interface. With the X6-RX, IF recorders can log both the digitized raw data and channels real-time sustaining rates over 2 GB/s. The X6-RX features four, 16-bit 160 MSPS A/Ds with dual digital downconverters (DDC). IF frequencies of up to 300 MHz are supported. The sample clock is from either a low-jitter PLL or external input. Multiple cards can be synchronized for sampling and downconversion. A Xilinx Virtex6 SX315T (LX240T at initial release) with 4 banks of 128MB DRAM provide a very high performance DSP core with over 2000 MACs (SX315T). The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at extremely high rates. Onboard DDC ASIC device, connected directly to the FPGA, provides up to 24 narrowband or 8 wideband channels with input from two A/D channels. The DDC performs complex or real downconversion, with flexible controls for mixing, filtering, decimation, output formats and data rates. Channels can be synchronized to support beam forming or frequency hopped systems. The X6 family power is less than 15W for typical operation. VITA 20 conduction cooling is used with a heat-spreader and sink are Ruggedization levels for wide-temperature operation and conformal coating are supported. The FPGA logic can be fully customized using VHDL and MATLAB using the Frame Work Logic toolset. The MATLAB BSP supports real-time hardware-inthe-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP cores for DDC, demodulation, and FFT are available. Software tools for host development include C++ libraries and drivers for Windows and Linux. Application examples demonstrating the module features and use are provided. Download the datasheet (PDF)
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Innovative Integration X5-G12 - PCI Express XMC Module with Dual channel 1 GSPS,12-bit Digitizer, Virtex5 FPGA and 512MB Memory Simple Type: Mezzanine Card The X5-G12 is an XMC I/O module featuring dual channels of 1 GSPS 12-bit digitizing with a Virtex5 FPGA computing core, DRAM and SRAM memory, and eight lane PCI Express host interface. A Xilinx Virtex5 SX95T or LX155T with 512 MB DDR2 DRAM and 4MB QDR-II memory provides a very high performance DSP core for demanding applications such RADAR and direct RF digitizing. The close integration of the analog IO, memory and host interface with the FPGA enables real-time signal processing at rates exceeding 300 GMAC/s. The X5 XMC modules couple Innovative's powerful Velocia architecture with a high performance, 8-lane PCI Express interface that provides over 1 GB/s sustained transfer rates to the host. Private links to host cards with >1.6 GB/s capacity using P16 are provided for system integration. The X5 family can be fully customized using VHDL and MATLAB using the FrameWork Logic toolset. The MATLAB BSP supports real-time hardware-in-the-loop development using the graphical, block diagram Simulink environment with Xilinx System Generator. IP logic cores are also available for SDR applications that provide from 16 to 4096 DDC channels. These IP cores transform the X5 modules into versatile receivers using proven logic cores from R-Interface and Innovative, ready for integration into your application. Download the datasheet (PDF)
Specifications
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Datasheet
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